An Adaptive-Rate Error Correction Scheme for NAND Flash Memory

Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing, Cheng-Wen Wu. An Adaptive-Rate Error Correction Scheme for NAND Flash Memory. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA. pages 53-58, IEEE Computer Society, 2009. [doi]

@inproceedings{ChenHHW09,
  title = {An Adaptive-Rate Error Correction Scheme for NAND Flash Memory},
  author = {Te-Hsuan Chen and Yu-Ying Hsiao and Yu-Tsao Hsing and Cheng-Wen Wu},
  year = {2009},
  doi = {10.1109/VTS.2009.24},
  url = {http://dx.doi.org/10.1109/VTS.2009.24},
  researchr = {https://researchr.org/publication/ChenHHW09},
  cites = {0},
  citedby = {0},
  pages = {53-58},
  booktitle = {27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA},
  publisher = {IEEE Computer Society},
  isbn = {978-0-7695-3598-2},
}