Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh. Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. In Diana Marculescu, Anand Raghunathan, Ali Keshavarzi, Vijaykrishnan Narayanan, editors, Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007. pages 195-200, ACM, 2007. [doi]
Abstract is missing.