A calibration-free 800MHz fractional-N digital PLL with embedded TDC

Mike Shuo-Wei Chen, David Su, Srenik Mehta. A calibration-free 800MHz fractional-N digital PLL with embedded TDC. In IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010. pages 472-473, IEEE, 2010. [doi]

Abstract

Abstract is missing.