Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology

Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee. Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014. pages 109-112, IEEE, 2014. [doi]

Abstract

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