On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh, Yaojun Zhang, Wujie Wen. On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. JETC, 9(2):16, 2013. [doi]

Abstract

Abstract is missing.