Zhi-Wei Chen, Jin-Tai Yan. Timing-constrained replacement using spare cells for design changes. In José Luis Ayala, Alex K. Jones, Patrick H. Madden, Ayse Kivilcim Coskun, editors, Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013. pages 347-348, ACM, 2013. [doi]
Abstract is missing.