Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains

Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig. Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. In Georges G. E. Gielen, editor, 2007 International Conference on Computer-Aided Design (ICCAD 07), November 5-8, 2007, San Jose, CA, USA. pages 370-375, IEEE, 2007. [doi]

Authors

Lei Cheng

This author has not been identified. Look up 'Lei Cheng' in Google

Deming Chen

This author has not been identified. Look up 'Deming Chen' in Google

Martin D. F. Wong

This author has not been identified. Look up 'Martin D. F. Wong' in Google

Mike Hutton

This author has not been identified. Look up 'Mike Hutton' in Google

Jason Govig

This author has not been identified. Look up 'Jason Govig' in Google