Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang. Memory Latency Reduction via Thread Throttling. In 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA. pages 53-64, IEEE, 2010. [doi]
Abstract is missing.