BIST TPG for SRAM cluster interconnect testing at board level

Chen-Huan Chiang, Sandeep K. Gupta. BIST TPG for SRAM cluster interconnect testing at board level. In 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan. pages 58-65, IEEE Computer Society, 2000. [doi]

Abstract

Abstract is missing.