Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation

De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan, Shih-Chieh Chang. Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(8):1285-1289, 2010. [doi]

Abstract

Abstract is missing.