Rituparna Choudhury, P. Rangababu. Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder. In Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh, editors, VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers. Volume 711 of Communications in Computer and Information Science, pages 742-750, Springer, 2017. [doi]
Abstract is missing.