Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture

Slo-Li Chu. Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture. In Vikram S. Adve, María Jesús Garzarán, Paul Petersen, editors, Languages and Compilers for Parallel Computing, 20th International Workshop, LCPC 2007, Urbana, IL, USA, October 11-13, 2007, Revised Selected Papers. Volume 5234 of Lecture Notes in Computer Science, pages 261-275, Springer, 2007. [doi]

Abstract

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