Arithmetic Bit-Level Verification Using Network Flow Model

Maciej Ciesielski, Walter Brown, André Rossi. Arithmetic Bit-Level Verification Using Network Flow Model. In Valeria Bertacco, Axel Legay, editors, Hardware and Software: Verification and Testing - 9th International Haifa Verification Conference, HVC 2013, Haifa, Israel, November 5-7, 2013, Proceedings. Volume 8244 of Lecture Notes in Computer Science, pages 327-343, Springer, 2013. [doi]

Abstract

Abstract is missing.