A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications

Michael Clinton, Rajinder Singh, Marty Tsai, Shayan Zhang, Bryan Sheffield, Jonathan Chang. A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 200-201, IEEE, 2018. [doi]