A Design-flow for implementing, validating and evaluating Machine-learning Classifiers on FPGAs

Jan Cordes, Maher Fakih. A Design-flow for implementing, validating and evaluating Machine-learning Classifiers on FPGAs. In Farshad Firouzi, Krishnendu Chakrabarty, Bahar Farahani, Fangming Ye, Vasilis F. Pavlidis, editors, Proceedings of the International Conference on Omni-Layer Intelligent Systems, COINS 2019, Crete, Greece, May 5-7, 2019. pages 86-91, ACM, 2019. [doi]

Abstract

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