A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA

Zhiqiang Cui, Zhongfeng Wang. A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]

Abstract

Abstract is missing.