Yosys+Odin-II: The Odin-II Partial Mapper with Yosys Coarse-grained Netlists in VTR - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Seyed Alireza Damghani, Kenneth B. Kent. Yosys+Odin-II: The Odin-II Partial Mapper with Yosys Coarse-grained Netlists in VTR. In Michael Adler, Paolo Ienne, editors, FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022. pages 157, ACM, 2022. [doi]

The following publications are possibly variants of this publication:

Odin-II Partial Technology Mapping for Yosys Coarse-grained Netlists in VTRSeyed Alireza Damghani, Kenneth B. Kent. fccm 2022: 1 [doi]

Improved language support for Verilog elaboration in Odin II and FPGA architecture benchmarking in the VTR CAD toolBipin Kumar Badri Narayanan, Lucas Cambuim, Konstantin Nasartschuk, Kenneth B. Kent, Paul G. Ploeger. pacrim 2015: 309-314 [doi]

A framework for verifying functional correctness in Odin IIJoseph C. Libby, Ashley Furrow, Paddy O'Brien, Kenneth B. Kent. fpt 2011: 1-6 [doi]

Hard block reduction and synthesis improvements in Odin IIBo Yan, Kenneth B. Kent. rsp 2015: 126-132 [doi]

Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD ResearchPeter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon. fccm 2010: 149-156 [doi]

Desired Footprint by Technology Mapping Modification using a Genetic Algorithm in Odin IISeyed Alireza Damghani, Jean-Philippe Legault, Kenneth B. Kent. rsp 2020: 1-7 [doi]

runs on WebDSL