Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas. Delay Analysis for an N-Input Current Mode Threshold Logic Gate. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012. pages 344-349, IEEE, 2012. [doi]
Abstract is missing.