High-performance multiplierless DCT architecture for HEVC

Anand D. Darji, Raviraj P. Makwana. High-performance multiplierless DCT architecture for HEVC. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. pages 1-5, IEEE, 2015. [doi]

Abstract

Abstract is missing.