3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic. 3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. In IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, May 19-22, 2024. pages 1-5, IEEE, 2024. [doi]

This author has not been identified. Look up 'Sudipta Das' in GoogleThis author has not been identified. Look up 'Samuel Riedel' in GoogleThis author has not been identified. Look up 'Marco Bertuletti' in GoogleThis author has not been identified. It may be one of the following persons:

Luca Benini

Look up 'Luca Benini' in GoogleThis author has not been identified. Look up 'Moritz Brunion' in GoogleThis author has not been identified. Look up 'Julien Ryckaert' in GoogleThis author has not been identified. Look up 'James Myers' in GoogleThis author has not been identified. Look up 'Dwaipayan Biswas' in GoogleThis author has not been identified. Look up 'Dragomir Milojevic' in Google

runs on WebDSL