3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs

Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic. 3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. In IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, May 19-22, 2024. pages 1-5, IEEE, 2024. [doi]

@inproceedings{DasRBBBRMBM24,
  title = {3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs},
  author = {Sudipta Das and Samuel Riedel and Marco Bertuletti and Luca Benini and Moritz Brunion and Julien Ryckaert and James Myers and Dwaipayan Biswas and Dragomir Milojevic},
  year = {2024},
  doi = {10.1109/ISCAS58744.2024.10558687},
  url = {https://doi.org/10.1109/ISCAS58744.2024.10558687},
  researchr = {https://researchr.org/publication/DasRBBBRMBM24},
  cites = {0},
  citedby = {0},
  pages = {1-5},
  booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, May 19-22, 2024},
  publisher = {IEEE},
  isbn = {979-8-3503-3099-1},
}