Experiments and analysis to characterize logic state retention limitations in 28nm process node

Sachin Dileep Dasnurkar, Animesh Datta, Mohamed H. Abu-Rahma, Hieu Nguyen, Martin Villafana, Hadi Rasouli, Sean Tamjidi, Ming Cai, Samit Sengupta, P. R. Chidambaram, Raghavan Thirumala, Nikhil Kulkarni, Prasanna Seeram, Prasad Bhadri, Prayag Patel, Sei Seung Yoon, Esin Terzioglu. Experiments and analysis to characterize logic state retention limitations in 28nm process node. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013. pages 1-6, IEEE Computer Society, 2013. [doi]

Abstract

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