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Near-threshold voltage design in nanoscale CMOS

Vivek De. Near-threshold voltage design in nanoscale CMOS. In Enrico Macii, editor, Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013. pages 612, EDA Consortium San Jose, CA, USA / ACM DL, 2013. [doi]

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