Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits

Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima. Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits. In DAC. pages 650-655, 1991. [doi]

Authors

Yutaka Deguchi

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Nagisa Ishiura

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Shuzo Yajima

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