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Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima. Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits. In DAC. pages 650-655, 1991. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic CircuitsNagisa Ishiura, M. Takahashi, Shuzo Yajima. dac 1989: 497-502 [doi]
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