Junyong Deng, Lin Jiang, Zecang Zeng. Design of Multi-phase Clock Generation and Selection Circuit for CDR. In Mark Burgin, Masud H. Chowdhury, Chan H. Ham, Simone A. Ludwig, Weilian Su, Sumanth Yenduri, editors, CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31 - April 2, 2009, Los Angeles, California, USA, 7 Volumes. pages 387-391, IEEE Computer Society, 2009. [doi]
Abstract is missing.