The following publications are possibly variants of this publication:
- A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT CalibrationAhmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. jssc, 49(1):50-60, 2014. [doi]
- 2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuitsWei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. isscc 2013: 248-249 [doi]
- An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generationDongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. aspdac 2017: 13-14 [doi]