High Level Testbench Generation for VHDL Models - researchr publication

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Stanislaw Deniziak, Krzysztof Sapiecha. High Level Testbench Generation for VHDL Models. In 6th Symposium on Engineering of Computer-Based Systems (ECBS 99), 7-12 March 1999, Nashville, TN, USA. IEEE Computer Society, 1999. pages 146-151, IEEE Computer Society, 1999. [doi]

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