Stanislaw Deniziak, Mariusz Wisniewski. A symbolic RTL synthesis for LUT-based FPGAs. In Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic. pages 102-107, IEEE Computer Society, 2009. [doi]
Abstract is missing.