A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS - researchr publication

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Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada. A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. In Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011. pages 75-76, IEEE, 2011. [doi]

Abstract is missing.

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