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Design of a high speed, low power synchronously clocked NOR-based JK flip-flop using modified GDI technique in 45nm technology

Krishnendu Dhar. Design of a high speed, low power synchronously clocked NOR-based JK flip-flop using modified GDI technique in 45nm technology. In 2014 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2014, Delhi, India, September 24-27, 2014. pages 600-606, IEEE, 2014. [doi]

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