Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor

Abhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning. Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. In ICCD. pages 143-148, 1997.

Abstract

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