Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra. Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. In 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France. pages 35-40, IEEE Computer Society, 2005. [doi]
Abstract is missing.