Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu. Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). In 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016. pages 139-146, IEEE, 2016. [doi]
Abstract is missing.