High speed V.32 trellis encoder/decoder implementation using FPGA

A. Dinh, R. Mason, J. Toth. High speed V.32 trellis encoder/decoder implementation using FPGA. In International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA. pages 295-298, IEEE, 1999. [doi]

Abstract

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