Yazhuo Dong, Wu Zhan, Xiqing Ye. Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources. In José Luis Ayala, Alex K. Jones, Patrick H. Madden, Ayse Kivilcim Coskun, editors, Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013. pages 343-344, ACM, 2013. [doi]
Abstract is missing.