Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs - researchr publication

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Rui Policarpo Duarte, Christos-Savvas Bouganis. Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs. In 2014 International Conference on ReConFigurable Computing and FPGAs, ReConFig14, Cancun, Mexico, December 8-10, 2014. pages 1-7, IEEE, 2014. [doi]

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