Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS

David E. Duarte, Suching Hsu, Keng L. Wong, Mingwei Huang, Greg Taylor. Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS. In Jacqueline Snyder, Rakesh Patel, Tom Andre, editors, IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings. pages 1-4, IEEE, 2010. [doi]

Abstract

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