David E. Duarte, Suching Hsu, Keng L. Wong, Mingwei Huang, Greg Taylor. Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS. In Jacqueline Snyder, Rakesh Patel, Tom Andre, editors, IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings. pages 1-4, IEEE, 2010. [doi]
@inproceedings{DuarteHWHT10,
title = {Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS},
author = {David E. Duarte and Suching Hsu and Keng L. Wong and Mingwei Huang and Greg Taylor},
year = {2010},
doi = {10.1109/CICC.2010.5617473},
url = {http://dx.doi.org/10.1109/CICC.2010.5617473},
researchr = {https://researchr.org/publication/DuarteHWHT10},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings},
editor = {Jacqueline Snyder and Rakesh Patel and Tom Andre},
publisher = {IEEE},
isbn = {978-1-4244-5758-8},
}