Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge. Cache implications of aggressively pipelined high performance microprocessors. In 2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings. pages 123-132, IEEE Computer Society, 2004. [doi]
Abstract is missing.