Subtype concept of VHDL for synthesis constraints

Wolfgang Ecker, Sabine März. Subtype concept of VHDL for synthesis constraints. In Gerald Musgrave, editor, Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992. pages 720-725, IEEE Computer Society Press, 1992. [doi]

Abstract

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