Florian Eibensteiner, Jürgen Kogler, Josef Scharinger. A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform. In IEEE Conference on Computer Vision and Pattern Recognition, CVPR Workshops 2014, Columbus, OH, USA, June 23-28, 2014. pages 637-644, IEEE, 2014. [doi]
Abstract is missing.