Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu. A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. In 2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015. pages 1-4, IEEE, 2015. [doi]
@inproceedings{ElkholySNEH15, title = {A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter}, author = {Ahmed Elkholy and Saurabh Saxena and Romesh Kumar Nandwana and Amr Elshazly and Pavan Kumar Hanumolu}, year = {2015}, doi = {10.1109/CICC.2015.7338376}, url = {http://dx.doi.org/10.1109/CICC.2015.7338376}, researchr = {https://researchr.org/publication/ElkholySNEH15}, cites = {0}, citedby = {0}, pages = {1-4}, booktitle = {2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015}, publisher = {IEEE}, isbn = {978-1-4799-8682-8}, }