Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation

K. Eshraghian, R. Sarmiento, P. P. Carballo, A. Núñez. Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation. Journal of Systems Architecture, 32(1-5):75-82, 1991. [doi]

Abstract

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