A 17ps time-to-digital converter implemented in 65nm FPGA technology

Claudio Favi, Edoardo Charbon. A 17ps time-to-digital converter implemented in 65nm FPGA technology. In Paul Chow, Peter Y. K. Cheung, editors, Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009. pages 113-120, ACM, 2009. [doi]

Abstract

Abstract is missing.