A parameterized timing-aware flip-flop merging algorithm for clock power reduction

Chaochao Feng, Daheng Yue, Zhenyu Zhao, Zhuofan Liao. A parameterized timing-aware flip-flop merging algorithm for clock power reduction. In 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018. pages 881-884, IEEE, 2018. [doi]

Abstract

Abstract is missing.