A parameterized timing-aware flip-flop merging algorithm for clock power reduction - researchr publication authors

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Chaochao Feng, Daheng Yue, Zhenyu Zhao, Zhuofan Liao. A parameterized timing-aware flip-flop merging algorithm for clock power reduction. In 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018. pages 881-884, IEEE, 2018. [doi]

This author has not been identified. Look up 'Chaochao Feng' in GoogleThis author has not been identified. Look up 'Daheng Yue' in GoogleThis author has not been identified. Look up 'Zhenyu Zhao' in GoogleThis author has not been identified. Look up 'Zhuofan Liao' in Google

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