A 28 GHz Hybrid PLL in 32 nm SOI CMOS

Mark A. Ferriss, Alexander Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman. A 28 GHz Hybrid PLL in 32 nm SOI CMOS. J. Solid-State Circuits, 49(4):1027-1035, 2014. [doi]

Abstract

Abstract is missing.