A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR

Thomas Froehlich, Vivek Sharma, Markus Bingesser. A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR. In Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010. pages 706-710, IEEE, 2010. [doi]

Abstract

Abstract is missing.