Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS - researchr publication authors

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Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, Keiji Kishine. Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS. In International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016. pages 261-262, IEEE, 2016. [doi]

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